1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device including MOS (metal oxide semiconductor) field effect transistors (hereinafter referred to as MOSFETs), and more particularly, it relates to a method of fabricating a semiconductor device, whose source and drain regions have triple diffusion structures, for attaining improvements of characteristics.
2. Description of the Background Art
FIG. 1 shows an LDD (lightly doped drain) type MOSFET, which has been announced by Tsang et al. as a structure for relieving an electric field in a drain part of a short channel transistor (see IEEE Transaction Electron Devices, Vol., ED-29, 1982, pp. 590-596).
An n-channel MOSFET having such an LDD structure as shown in FIG. 1 is hereinafter referred to as "first prior art". Referring to FIG. 1, the n-channel MOSFET comprises a p-type semiconductor substrate 1 and a gate electrode 3 of polysilicon formed thereon through a gate insulating film 2. Sidewall spacers 4 of oxide films are formed along sidewalls of the gate electrode 3. At the surface of the semiconductor substrate 1, a source region 5 and a drain region 6 are formed on both sides of the gate electrode 3. The source region 5 is formed by a high-concentration n-type impurity diffusion layer 5a of 10.sup.18 /cm.sup.3 to 10.sup.20 /cm.sup.3 and a low-concentration n-type impurity diffusion layer 5b of 10.sup.17 /cm.sup.3 to 10.sup.18 /cm.sup.3, while the drain region 6 is formed by a high-concentration n-type impurity diffusion layer 6a and a low-concentration n-type impurity diffusion layer 6b. Parts of the low-concentration n-type impurity diffusion layers 5b and 6b extend into a region which is located immediately under the gate electrode 3 by several hundred .ANG. beyond the ends thereof.
The function of the LDD structure according to the first prior art is now described with reference to FIG. 1. The source region 5 and the semiconductor substrate 1 of the n-type MOSFET are set at potentials of 0 V, for example, while the drain region 6 is supplied with a source voltage of 5 V, for example. Therefore, the p-n junction between the n-type impurity diffusion layers 6a and 6b of the drain region 6 and the p-type semiconductor substrate 1 is reverse-biased, to generate a high electric field.
Such a drain field is relieved as the width of a depletion layer is increased. The width .omega. of such a depletion layer of the p-n junction is as follows: ##EQU1## where N.sub.A represents acceptor concentration, N.sub.D represents donor concentration, .epsilon.s represents the dielectric constant of the semiconductor, and o represents the amount of charges. When the n-type impurity concentration is extremely higher than the p-type impurity concentration, i.e., N.sub.D &gt;N.sub.A, the width .omega. of the depletion layer is as follows: ##EQU2## When the n-type impurity concentration is equal to the impurity concentration of the p-type semiconductor substrate, i.e., N.sub.A =N.sub.D, the width .omega. of the depletion layer is as follows: ##EQU3## Thus, it is understood that the width .omega. of the depletion layer is increased as the donor concentration N.sub.D is reduced, to relieve the field strength.
On the basis of the aforementioned concept, the LDD-MOSFET according to the first prior art as shown in FIG. 1 is provided with the low-concentration n-type impurity diffusion layers 5b and 6b along the p-n junction parts between the semiconductor substrate 1 and the high-concentration n-type impurity diffusion layers 5a and 6a, to relieve the field strength.
The working condition of the LDD-MOSFET is now described with reference to FIGS. 2A and 2B. The operation of such a transistor is divided into that in a pentode region (FIG. 2A) where a drain voltage V.sub.D is greater than a gate voltage V.sub.G and that in a triode region (FIG. 2B) where the gate voltage V.sub.G is extremely greater than the drain voltage V.sub.D. In the pentode region shown in FIG. 2A, a high-resistance depletion layer 8 is formed between an inversion layer 7 and the drain region 6. In this case, driving ability of the transistor is reduced by the resistance, which is parasitic resistance, of the low-concentration n-type impurity diffusion layer 5b of the source region 5, that of the depletion layer 8 along the drain region 6, and that of the low-concentration n-type impurity diffusion layer 6b of the drain region 6, in addition to the resistance of a channel formed by the inversion layer 7. In the triode region shown in FIG. 2B, on the other hand, the driving ability of the transistor is reduced by the resistance, which is parasitic resistance, of the n-type impurity diffusion layer 5a of the source region 5, and that of the n-type impurity diffusion layer 6a of the drain region 6.
In the drain structure of the LDD-MOSFET according to the first prior art, further, hot carriers having higher energy than that in a thermal equilibrium state are produced on the surface of the low-concentration n-type impurity diffusion layer 6b. Such hot carriers are injected into the sidewall spacer 4 which is formed along the sidewall of the gate electrode 3, to deplete the surface of the n-type impurity diffusion layer 6b of the drain region 6 and increase the resistance of this region. Thus, the driving ability of the MOSFET is further deteriorated.
FIG. 3 shows another conventional LDD-MOSFET (hereinafter referred to as "second prior art") disclosed in Japanese Patent Laying-Open No. 1-212471, for example, which has been proposed in order to solve the aforementioned problem of the first prior art. Referring to FIG. 3, low-concentration n-type impurity diffusion layers 5b and 6b of source and drain regions 5 and 6 are overlapped with a gate electrode 3, while ends of high-concentration n-type impurity diffusion layers 5a and 6a are aligned with those of the gate electrode 3.
In the structure of the LDD-MOSFET according to the second prior art, the low-concentration n-type impurity diffusion layers 5b and 6b are completely covered with the gate electrode 3. Therefore, carrier concentration on the surfaces of the low-concentration impurity diffusion layers 5b and 6b is increased by a voltage which is applied to the gate electrode 3, to suppress increase of the regulated resistance in the source region 5. Further, a region of the drain region 6 generating a high electric field is located not immediately under the sidewall spacer 4 but immediately under the gate electrode 3, whereby no hot carriers are injected into the sidewall spacer 4. Consequently, the low-concentration impurity diffusion layer 6b is prevented from depletion of its surface.
FIGS. 4A and 4B show carrier production rate distributions in the first prior art and the second prior art, for clearly illustrating difference between hot carrier production states thereof. FIGS. 5A and 5B show transistor characteristics of the first prior art and the second prior art respectively.
When the low-concentration n-type diffusion layers 5b and 6b of the second prior art are prepared from phosphorus, in particular, the regions thereof are spread by heat treatment since phosphorus has a large diffusion coefficient. If the width of the gate electrode 3 is reduced as the result of high integration, therefore, it is impossible to attain sufficient lengths of the low-concentration n-type impurity diffusion layers 5b and 6b in order to ensure an effective channel length, and a sufficient field strength relieving effect cannot be attained since the high-concentration n-type impurity diffusion layers 5a and 6a reach ends of the gate electrode 3. If the high-concentration n-type impurity diffusion layers 5a and 6a are reduced in concentration in order to avoid this, the current driving characteristic of the transistor is problematically deteriorated. This problem is unavoidable in an LDD structure employing double diffusion layers.
FIG. 6 shows still another conventional LDD-MOSFET (hereinafter referred to as "third prior art") having triple diffusion structures disclosed in Japanese Patent Laying-Open No. 61-139070, for example, which has been proposed in order to solve the aforementioned problem of the second prior art.
Referring to FIG. 6, the MOSFET according to the third prior art is formed on an active region of a p-type semiconductor substrate 11, which is isolated by isolating regions 12. This MOSFET has a gate electrode 14, which is formed on the semiconductor substrate 11 with a gate insulating film 13 interposed therebetween, and source and drain regions 15 and 16, which are formed on the surface of the semiconductor substrate 11. Sidewall spacers 17 are formed on both side portions of the gate electrode 14. The surfaces of the gate electrode 14, the sidewall spacers 17 and the isolation regions 12 are covered with interlayer isolation films 18, while the source and drain regions 16 communicate with aluminum wires 20 through contact holes 19 which are formed in prescribed positions of the interlayer isolation films 18. The source and drain regions 15 and 16 are formed by low-concentration n-type impurity layers 15c and 16c which are overlapped with the gate electrode 13, medium-concentration n-type impurity layers 15b and 16b which are located immediately under the sidewall spacers 17, and high-concentration n-type impurity layers 15a and 16a which are adjacent thereto.
FIGS. 7A to 7E show a method of fabricating the MOSFET according to the third prior art. First, phosphorus ions are implanted through a mask of the gate electrode 14 from a direction which is substantially perpendicular to the surface of the semiconductor substrate 11, to form the low-concentration n-type impurity layers 15c and 16c (FIG. 7A). In this case, in order to prevent so-called channeling, the direction of ion-implantation should be inclined about 7.degree. from the normal direction.
Then, the sidewall spacers 17 are formed on both sidewalls of the gate electrode 14 (FIG. 7B), and arsenic ions are perpendicularly implanted with respect to the surface of the semiconductor substrate 11 through masks of the sidewall spacers 17, to form the medium-concentration n-type impurity layers 15b and 16b (FIG. 7C). Then, heat treatment is performed to diffuse the low-concentration n-type impurity layers 15c and 16c and the medium-concentration n-type impurity layers 15b and 16b so that the respective n-type impurity layers move toward the center of the channel region, thereby attaining the state shown in FIG. 7D. Thereafter arsenic ions are further implanted substantially perpendicularly to the semiconductor substrate 11 through masks of the gate electrode 14 and the sidewall spacers 17, to form the high-concentration n-type impurity layers 15a and 16a (FIG. 7E). The direction should be inclined about 7.degree. C. from the normal direction also in this case for preventing channeling.
The problems of the first prior art and the second prior art are solved so far as it is possible to overlap the low-concentration n-type impurity layers 15c and 16c with the gate electrode 14 and to form the medium-concentration n-type impurity layers 15b and 16b immediately under the sidewall spacers 17 in high accuracy in the LDD-MOSFET of the triple diffusion structure according to the third prior art.
In the method shown in FIGS. 7A to 7E in relation to the third prior art, however, the low-concentration n-type impurity layers 15c and 16c are overlapped with the gate electrode 14 and the medium-concentration n-type impurity layers 15b and 16b are formed immediately under the sidewall spacers 17 through thermal diffusion steps. Thus, it is extremely difficult to attain desired impurity concentration distributions in high accuracy.
Particularly in fabrication of a semiconductor memory device such as a CMOS (complementary MOS) device having n-channel and p-channel MOSFETs formed on the same semiconductor substrate, it is impossible to attain required concentration distributions through heat treatment steps with widths of sidewall spacers which are common to the MOSFETs in the fabrication steps according to the third prior art, since impurity ions implanted for forming source and drain regions of the MOSFETs have different diffusion coefficients. Namely, diffusion coefficients of boron ions (B.sup.+) and BF.sub.2 ions which are employed for forming source and drain regions of the p-channel MOSFET are larger than those of phosphorus ions and arsenic ions which are employed for forming source and drain regions of the n-channel MOSFET, and hence the effective channel length is reduced due to significant progress of diffusion if the sidewall spacers are identical in width to each other. Therefore, sidewall spacers for the p-channel MOSFET must be formed independently of those for the n-channel MOSFET to have larger widths. Thus, the fabrication steps are complicated.